Description: Title: Pre-Silicon Verification Engineer Contract Length: Initial 6-month contract ( ...
22 days ago
Description: Senior Design Verification Engineer SV/UVM Contract Long Term ... francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using ...
13 days ago
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
22 days ago
Description: Role: CAD/EDA Engineer Silicon Design/Verification Infrastructure Location: San Francisco, CA / ... SoC/IP design and/or verification infrastructure development. Proficiency in modern ...
28 days ago