... (SDC) for complex chip-level ASIC designs Perform static timing analysis (STA ... with RTL, architecture, and physical design teams on clock structures and ...
13 hours ago
... : Chip-Level Timing Constraint Development Engineer Location: San Jose, CA Onsite ... validating timing constraints for complex ASIC designs at the chip level. Your ... teams, including RTL designers, physical design engineers, and verification teams, to ensure ...
15 hours ago