Description: Position: Senior ASIC Design Engineer- Emulation (HAPS Engineer) Location: San Jose, CA (Complete ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... engage in block-level RTL design or block or top
18 days ago
... Computer Engineering with 7+ years of ASIC or related experience or Master ... Computer Engineering with 5+ years of ASIC or related experience Experience with ... /Tempus Understanding of related digital design concepts (eg. clocking and async ...
5 days ago
... Description: Title: ASIC Verification Engineer - Hybrid Mandatory skills: UVM, UVM design verification, UVM ... I/O SOC, UVM test bench development, design verification, test plan, test verification ... of a block(s) of complex ASICs and/or IP cores for ...
26 days ago
Description: Job Title Sr. Package Design Engineer ASIC/SOC Job Location: San Jose, ... : Sr. Package Design Engineer We are seeking a highly experienced Package Design Engineer with 7+ years ...
4 days ago
Description: Job Title: Physical Design Engineer Custom ASIC / SoC Hybrid San Jose, CA ... assistance available Position Overview Physical Design Engineer: We are seeking a hands-on ...
4 days ago
... : DFX RTL Design Engineer - Hybrid Mandatory skills: RTL, RTL design, RTL checks, RTL ...
26 days ago
... own major portions of the design and implementation of blocks to ... . Work with verification and physical design teams to achieve high quality ... design and successful tape out. XXgn ...
a month ago
... .Worked on at least 2 PCB designs Skills required: Bachelors in Electrical ...
19 days ago
... know your interest. POSITION PCB DESIGN ENGINEER LOCATION-SAN JOSE CA (Onsite ... with lab bring up and design validation.Knowledge of high speed ... SerDes (> 1G) interfaces, high speed design and signal integrity principlesKnowledgeable in ...
19 days ago
... : Full time role Senior ASIC Program Manager/Technical Program Manager ... Negotiable): 7+ years in ASIC and/or foundry environments (design, verification, fab, ... packaging, testing). 5+ years program/project management in hardware/ASIC ...
12 days ago
... : Job Title: Senior Front-End ASIC Engineer Job Location: San Jose, CA ... is seeking a Senior Front-End ASIC Engineer to join their elite engineering ...
4 days ago
... product and engineering teams to design AI and LLM solutions and ... support business objectives. Design, develop and deliver AI/ML ...
5 days ago
Description: Job Title: STA Engineer Location: San Jose ,CA Contract: ... Doing: Technical: Being a member of design team who oversees fullchip STA ... SDCs and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
6 days ago
... Keywords: HAPS FPGA Prototyping Emulation Design What candidate will Be Doing ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ...
6 days ago
... management, and user support Layout design support and PCELL development Work ... with global design centers Must-Have Skills: 12 ...
6 days ago
... Keywords: HAPS FPGA Prototyping Emulation Design What candidate will Be Doing ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ...
11 days ago
... Keywords: HAPS FPGA Prototyping Emulation Design What candidate will Be Doing ... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ...
11 days ago
Description: Key Responsibilities * Design, develop, and maintain scalable distributed ... using advanced multi-threading techniques * Design and manage efficient, scalable database ...
18 days ago
Description: Position: STA Engineer- Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
18 days ago
... Job Title: Static Timing Analysis Engineer Location: San Jose ,CA (Onsite ... Technical Requirement: Being a member of design team who oversees fullchip STA ... SDCs and works with physical design and DFT teams to close ... also do block level RTL design or block or top- ...
24 days ago