Description: Physical Design Engineer(Onsite) First preference : SAN JOSE, ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
5 days ago
Description: Physical Design Engineer Contract First preference : CA Second ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
5 days ago
Description: Job Title: FPGA Engineer Location: San Jose, CA Experience: ... C2C Key Responsibilities: Design and implement FPGA architectures using VHDL/Verilog ... translate requirements into specifications. Support FPGA integration, testing, and documentation. ...
3 days ago
Description: Job Title: FPGA Engineer Location: San Jose, CA, USA ... Rate: DOE Key Responsibilities: Design and implement FPGA architectures using VHDL/Verilog ... translate requirements into specifications.Support FPGA integration, testing, and documentation. ...
6 days ago
Description: Job Title: SoC Lead Engineer Location: San Jose, CA Company: ... (ARM cores, SMMU, GIC) and design clock/reset architectures.Collaborate with ... , Lint/CDC checks, and support FPGA/emulation efforts.Key Skills: ARM ...
5 days ago
Description: Job Title - Design Verification Engineer (GPU) Duration 6+ Months Location: San ... , CA Description As a GPU Design Verification Engineer, your talents will ensure the ...
6 days ago
Description: Job Title - Design Verification Engineer (GPU) Duration 9 + Month (With the ... w2 Description As a GPU Design Verification Engineer, your talents will ensure the ...
6 days ago
... -efficiency of big data pipelines. 7. Design and development of databases for ...
2 days ago