... Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA ... Doing: Technical: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to ... to also do block level RTL design or block or top-level ...
5 days ago
... to join its Memory Interconnect Design team in either San Jose ... Engineer will report to the Director of Design Engineering and take a key ...
2 days ago