... : Job Title: Senior ASIC Design Engineer Location: San Jose, CA ... million gate SoC designs onto prototyping platforms, creating design partitions, FPGA ... engage in block-level RTL design or block or top- ... . Collaborate with Software, Design, and Verification t
3 days ago
... an opening for Mixed-Signal Design Verification Engineer with our Client ... Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc.Good understanding of digital design for mixed signal control loops ...
11 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, ... : Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc. Good understanding of digital design for mixed signal control loops ...
30 days ago
... ,UVM Debug RTL and Gate simulations and work with design engineers to ...
7 days ago
... -million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds ... to engage in block-level RTL design or block or top-level ... IP integration. Collaborate with Software, Design, and V
a day ago
... functionality of a digital design environment for FPGA design using Verilog and UVM ... . Collaborate closely with RTL designers to debug and resolve design issues. Ind
28 days ago
... : Strong knowledge of System-Verilog RTL coding, including state machines, adders ... logic. Solid understanding of digital design for mixed-signal control loops ...
29 days ago
... will focus on verifying FPGA designs in routers, ensuring all functionalities ... verification, and collaborating closely with RTL designers to debug failures. The ...
27 days ago