Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA ... Doing: Technical: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to ... to also do block level RTL design or block or top-level ...
a day ago
... brands-everything they need to design and deliver exceptional digital experiences ...
4 days ago
Description: Senior Staff AI Engineer LLM inference optimization Roles and Responsibilities: Design and ... -concept projects to evaluate architectural designs for functionality, performance, security, and ...
a day ago
$50
$60
an hour
... for a Senior QA Engineer in Santa Clara, CA. Responsibilities: Design, develop, and ...
2 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
3 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
5 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
5 days ago
... ) for complex chip-level ASIC designs Perform static timing analysis (STA ... with RTL, architecture, and physical design teams on clock structures and design intent ...
6 days ago
... timing constraints for complex ASIC designs at the chip level. Your ... cross-functional teams, including RTL designers, physical design engineers, and verification teams ...
6 days ago
... ) Contract(No OPT) Job Description: Senior level (5 to 8 years) experience in ... write code and understand the design of a system.Strong knowledge of ...
a day ago