Description: Job Title: Senior Engineer Location: San Jose, CA (5 days ... 6+ Months Job Description Design Verification expertise in System Verilog /UVM Unit/Module ... Experience in test planning and debugging complex designs Full silicon design lifecycle ...
18 days ago
Description: Product Test Engineering Location: San Jose, CA ... for space applications? As a Product Engineer for Hybrid DC-DC converters ...
27 days ago
... : Experience working as a Thermal Validation Engineer for electromechanical products.Telecom equipment ... advantage.Good knowledge about telecom test standards GR, NEBS etc.Setting ... lab for thermal and acoustics tests (Thermocouple installation, wind tunnel ...
11 days ago
... Immediate hiring for Senior Design Verification Engineer with one of our ... someone. Job title: Senior Design Verification Engineer Location: San Jose, CA ... Design Verification expertise in System Verilog /UVM Unit/Module level VerificationExperience in test ...
14 days ago
... : Experience working as a Thermal Validation Engineer for electromechanical products.Telecom equipment ... advantage.Good knowledge about telecom test standards GR, NEBS etc.Setting ... lab for thermal and acoustics tests (Thermocouple installation, wind tunnel ...
19 days ago
... for Design Verification Engineer in San Jose, CA: Job Title: Design Verification Engineer Job ... time Job Duties: Collaborate with design and development teams to understand ... , and tools for verifying the design. Develop standards and guidelines to ...
4 days ago
... are looking for Software Development Engineer, Release - Remote / Telecommute for ... , CA Job Title: Software Development Engineer, Release - Remote / Telecommute Job ... new training workloads and expanding test coverageEnsure the stability and releasability ...
13 days ago
... testing methods, develop test plans, and design GSE for risk mitigation ... demonstration needsDevelop assembly and test processes for sub-systems and vehicle integration ... to testing processes and methodologiesAssist system team in development of ...
15 days ago
... : Title: Verification Engineer - Hybrid Description: ... of a team of design verification team, working ... design element within the context of the block, chip and overall system ... . Candidate will be participating in the UVM testbench development, test ...
20 days ago
... : "Remote Job Description You will design, develop, and maintain BI solutions ... to leadership and stakeholders. Responsibilities: Design, develop, and maintain end-to ...
6 days ago
Description: Solid understanding of digital design concepts, RTL design (Verilog/VHDL), and computer ...
12 days ago
... Silicon Power Analysis and Optimization Engineer for our client in San ... : Silicon Power Analysis and Optimization Engineer Job Location: San Jose, CA ... in low power ASIC design.Proficiency in RTL design languages like Verilog ...
14 days ago
... Role We're seeking a Packaging Engineer to design, develop, and validate packaging ... and process improvements. Key Responsibilities Design sterile and non-sterile packaging ...
27 days ago
... : Job Title: Emulation & Functional Verification Engineer Location: San Jose, CA (Onsite ... /SoC-level validation.Perform Design Functional Verification using System Verilog and UVM ... methodologies.Engage in both software (test) and ...
28 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
a day ago
... brands-everything they need to design and deliver exceptional digital experiences ...
a day ago
... brands-everything they need to design and deliver exceptional digital experiences ...
a day ago
... brands-everything they need to design and deliver exceptional digital experiences ...
2 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
2 days ago
... brands-everything they need to design and deliver exceptional digital experiences ...
2 days ago