Description: Package Design Engineer in the US, please share ... Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
12 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
6 days ago
... package design (8+) experienceUnderstanding of substrate manufacturing design rule and assembly rulePossess Flip Chip Package Design ...
11 days ago