... an opening for Mixed-Signal Design Verification Engineer with our Client ... Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc.Good understanding of digital design for mixed signal control loops ...
11 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, ... : Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc. Good understanding of digital design for mixed signal control loops ...
a month ago