Description: We're seeking an experienced ASIC Design Verification Engineer with 8 10 years in SystemVerilog/UVM and a strong track record of first-pass silicon success. You'll define and execute SoC-level verification plans, develop UVM-based testbenches ...
3 days ago
Description: Title: SOC Design Verification Engineer Location: Santa Clara, CA Duration: 6+ Months Job Description: Basic Qualifications: Bachelor's degree in electrical / communications engineering or computer science 3 to 5+ years of experience in ...
23 days ago