Description:
We're seeking an experienced ASIC Design Verification Engineer with 8 10 years in SystemVerilog/UVM and a strong track record of first-pass silicon success. You'll define and execute SoC-level verification plans, develop UVM-based testbenches, and drive coverage closure. Proficiency in scripting (Python/TCL/Perl/Shell) and experience with EDA tools is required. Preferred skills include GPU/CPU verification, high-speed interface testing (PCIe, DDR, Ethernet), and familiarity with revision control
Sep 2, 2025;
from:
dice.com