... : Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will work closely with design engineers to develop and execute verification pla
28 days ago
... in System Verilog and UVM verification methodologyExperience with Linux operating systemExperience ... with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps ...
13 days ago
... Engineer Location: Santa Clara, CA, 95051 Duration:12 Months Job Description: Principal ...
8 days ago