... Description: Title: Silicon Design Engineer - Onsite Description: SENIOR SILICON DESIGN ENGINEER THE ROLE: This ... n Route, timing, and Physical Verification THE PERSON: Strong communication skills ... out teams RESPONSIBILTIES: This engineer will work on high- ...
15 days ago
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
10 days ago