... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex digital IPs ... silicon. Key responsibilities - Own verification of one or more IPs ...
2 days ago
Description: Urgent Opening:DesignVerificationEngineer Job Title:DesignVerificationEngineer Experience: 10+ years Location: San Jose, CA (or other US locations) Job Type: Full-time/Contract KeyRequirements: - Experience working on Subsystems on a Chip ( ...
23 days ago