Description:
Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in IP and subsystemlevel verification using SystemVerilog and UVM. The engineer will own verification of complex digital IPs/subsystems, drive coverage closure, and collaborate closely with RTL, architecture, and validation teams to deliver highquality silicon. Key responsibilities - Own verification of one or more IPs or subsystems (e.g., interconnect, memory, I/O, compute blocks) from testplan to coverage cl
Nov 26, 2025;
from:
dice.com