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Jobs and careers for fpga rtl design engineer in Santa Clara (3 jobs)

Lead fpga verification engineer with uvm /verilog system-active requirement
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming ...
2 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands ...
5 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming ...
9 days ago

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