What
Where
0
Home Browse jobs About us Contacts
  1. Home
  2. Santa Clara
  3. Python ai ml engineer
What
Where

Jobs and careers for python ai ml engineer in Santa Clara (3 jobs)

Lead fpga verification engineer with uvm /verilog system-active requirement
Company
Period
Schedule
Employment
Source
Location
Sort by:

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... problem-solving Scripting experience in Python or Perl Knowledge of Verilog ...
6 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... and problem-solvingScripting experience in Python or PerlKnowledge of Verilog and ...
9 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... problem-solving Scripting experience in Python or Perl Knowledge of Verilog ...
13 days ago

Get new python ai ml engineer jobs in Santa Clara by email

By creating a job alert, you agree to our Terms You can change your consent settings at any time by unsubscribing or as detailed in our terms.