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Jobs and careers for senior python engineer in Santa Clara (3 jobs)

Lead fpga verification engineer with uvm /verilog system-active requirement
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... problem-solving Scripting experience in Python or Perl Knowledge of Verilog ...
2 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... and problem-solvingScripting experience in Python or PerlKnowledge of Verilog and ...
5 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... problem-solving Scripting experience in Python or Perl Knowledge of Verilog ...
9 days ago

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