Description: Job Responsibilities: Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVMDevelop constrained-random, metric-driven test plans and strategies to verify FPGAs ...
19 days ago
Description: 3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one ...
24 days ago
... work closely with HW Engineers to automate design and simulation flows. Responsibilities ... AWS.Collaborate with HW Engineers to automate design and simulation flows.Requirements ...
9 days ago
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