... in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.3+ years' experience ... following areas along with functional verification - SV Assertions, Formal, Emulation ... tools and flows for verification environments.Experience in architecting ...
27 days ago
... to a dynamic DV teamCreate reusable Verification IP
23 days ago
... a High-Speed Analog EDA/CAD Engineer with to support SiGE and ... High-Speed Analog EDA/CAD Engineer to support and develop SiGe ... the high speed analog ASIC design team. The engineer will be hands ... , layout, archive and tapeout. The engineer must be an expert in a
9 days ago
... seeking a High-Speed Analog Engineer with EDA/CAD engineering to ... Seeking an High-Speed Analog Engineer to support and develop SiGe ... the high speed analog ASIC design team. The engineer will be hands ... layout, archive and tapeout. The engineer must be an expert
13 days ago
... seeking a High-Speed Analog Engineer with EDA/CAD engineering to ... Seeking an High-Speed Analog Engineer to support and develop SiGe ... the high speed analog ASIC design team. The engineer will be hands ... layout, archive and tapeout. The engineer must be an expert
15 days ago
... seeking a High-Speed Analog Engineer with EDA/CAD engineering to ... Seeking an High-Speed Analog Engineer to support and develop SiGe ... the high speed analog ASIC design team. The engineer will be hands ... layout, archive and tapeout. The engineer must be an expert
16 days ago
... transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso ...
21 days ago