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Chip Desgner/Packaging

eTeam, Inc.
Santa Clara Full-day Temporary

Description:

Job Title: Chip Desgner/Packaging Job Location: Santa Clara, CA (Hybrid) IC Packaging & Chiplet Integration : 2.5D/3D packaging, flip-chip bonding, TSV, hybrid bondingSemiconductor Processing : BEOL/FEOL integration, advanced interconnects, thin-film deposition (PVD, PECVD, ALD, CVD)Design & Simulation : Siemens NX, Cadence, ANSYS, EasyEDA, ThermoCalcHigh-Speed I/O & Signal Integrity : Impedance control, power/signal integrity, substrate optimizationProcess Development & Metrology : DOE, SPC,
May 1, 2025;   from: dice.com
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