Description:
Requirements: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.Experience in EDA tools and scripting (Pytho
May 8, 2025;
from:
dice.com