Description:
Title: ASIC Verification Engineer - Hybrid Mandatory skills: UVM, UVM design verification, UVM verification, UVM environment, AISC, SOC, AISC verification, SOC verification, DV tools, DV methodologies, CPU, I/O, Cadence, Synopsys Verification tools, Synopsys, Verdi, System Verilog, IP, I/O SOC, UVM test bench development, design verification, test plan, test verification Description: Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O
Jun 3, 2025;
from:
dice.com