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Static Timing Analysis? Engineer

Apolis
San Jose Full-day Full-time

Description:

Job Title: Static Timing Analysis Engineer Location: San Jose ,CA (Onsite) Contract: 12+ MonthsWhat candidate will Be Doing: Technical Requirement: Being a member of design team who oversees fullchip STA/ SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes ba
Jun 5, 2025;   from: dice.com

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