Description:
About the Role:Seeking an experienced STA/SDC engineer to own block and full-chip constraints, perform Static Timing Analysis (PrimeTime/Tempus), and collaborate with design and physical design teams for timing closure. Key Skills: Strong expertise in STA and SDC constraints (functional & test modes) Experience with PrimeTime, Tempus, and synthesis tools (Synopsys DC/DCG/FC) Verilog/SystemVerilog design knowledge CDC/glitch analysis (Spyglass CDC), Formal Verification (Formality, LEC) Scripting
Jun 26, 2025;
from:
dice.com