Description:
Title: Hardware Design Engineer (RTL to GDS Flow) Location: Hybrid (3days/week) - Silicon Valley, CA Pay rate: $80-85/Hr. We are seeking a highly skilled and motivated engineer with deep expertise in RTL-to-GDSII flows, specifically using Synopsys Fusion Compiler and RTL Architect (RTLA). This role is pivotal in driving synthesis quality, power-performance-area (PPA) optimization, and methodology development for advanced node SoC designs. Key Responsibilities Own and optimize RTL-to-GDSII implem
Sep 10, 2025;
from:
dice.com