Description:
Job Description: Pay Range: $64hr - $67hr Responsibilities: Develop and execute comprehensive verification plans for FPGA designs. Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog). Write and debug test cases to verify functionality, performance, and corner cases. Perform code coverage and functional coverage analysis. Identify and debug issues, working closely with design engineers to resolve them. Document verification results and pr
Sep 12, 2025;
from:
dice.com