... 10+ years of senior Pre-silicon verification engineer with PCIE physical, link layer ... state of the art of verification techniques, including assertion and ... metric-driven verification. Require familiarity with verification management tools. Prior ...
17 days ago
Description: Title: Pre-Silicon Verification Engineer Contract Length: Initial 6-month contract ( ...
11 days ago
... opportunity to: This type of verification can span simulation and emulation ... the same team in most silicon companies. Even in our company ...
a day ago
Description: Contract Length: Initial 6-month contract (potential to go 18-months) Location:100% onsite in either Sunnyvale, CA, San Francisco, CA or Austin TX Industry: Social Media Work Authorization: Prefers G.C or U.S Citizen. Minimum Requirements ...
11 days ago
$70
$80
an hour
Description: Silicon DV Engineer II BC forward is currently ... seeking the initiative to take Silicon ... DV Engineer for a (Remote) Location. Position Title: Silicon DV Engineer Location ...
24 days ago
... : Summary: The main function of Silicon Validation Engineer is to run, triage ... , and maintain silicon system regressions and report ...
10 days ago
Description: Role: Silicon Validation Engineer Location: Mountain View, CA Duration: ...
5 days ago
Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ...
17 days ago
Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... and implement IP/SoC verification plans, build verification test benches to enable ... tests based on verification test plan Drive Design Verification to closure based ...
18 days ago
Description: Title: Verification Engineer Location: Sunnyvale, CA Type: Contract ... : The main function of the Verification Engineer is to work with a group ... researchers and engineers to own the electrical system level verification of client ...
11 days ago
... : The main function of the Verification Engineer is to work with a group ... researchers and engineers to own the electrical system level verification of client ... -the-art systems. Using verification skills to define verification requirements, create test ...
10 days ago
Description: Verification Engineer IV Sunnyvale CA (Onsite) 6 months ( ... : The main function of the Verification Engineer is to work with a group ... -the-art systems.The engineer will define verification requirements, create test ca
11 days ago
... Description: Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS Location: ... an experienced Senior Design Verification Engineer with expertise in Ethernet ... - Collaborate with design engineers to resolve verification issues - Strong understa
10 days ago
... are looking for Senior Design Verification Engineer for our client in Ottawa ... , ON Job Title: Senior Design Verification Engineer Job Location: Ottawa, ON Job ... /Maintain tests for functional verification with UVM verification at the subsystem level ...
19 days ago
... : Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... a Senior Staff System IP Design Verification Contractor you will contribute to ... the functional verification of System IP including coherent ...
24 days ago
... is looking for an Design Verification Engineer. Position type: Contract Duration: 12 ... , CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications ... .Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
3 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key ... , Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good ...
17 days ago
Description: Senior Design Verification Engineer SV/UVM Contract Long Term ... francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using ...
2 days ago
Description: Position Title: Design Verification Engineer Location: Mountain View, CA - Onsite ... Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
2 days ago
Description: Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14+ ... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
4 days ago
- 1
- 2