... : NVIDIA is seeking elite ASIC Verification Engineers to verify the design and ...
4 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
18 hours ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
4 days ago
... now looking for a Senior ASIC Verification Engineer for our Coherent High Speed ...
5 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
5 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
6 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
7 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
10 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
11 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
12 days ago
Description: Job Title: GLS Design Verification Engineer Location: Canada Remote Duration / Term: 6+ ...
13 days ago
... opening for Mixed-Signal Design Verification Engineer with our Client at San ...
14 days ago
Description: Role: Pre/Post Silicon Validation Location: Sunnyvale CA or ... plan development, and execution Execute silicon bring-up and validation activities ... performance characterization on pre-silicon platforms and post-silicon validation boards Able ...
6 days ago
... in architecting and implementing Design Verification infrastructure and executing the complete ... the development of UVM based verification environments from scratchExperience with ... Design verification of Data-center applications ...
6 days ago
... SV/UVM. Experience in complete verification cycle which includes development of ...
10 days ago
... : Architect block and full-chip verification environments using HVLs and constrained ... simulations and work with design engineers to verify fixes. Write diagnostics ...
10 days ago
... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
13 days ago
... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
24 days ago
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
27 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) ... : Engineering Required Skills: Pre-silicon verification / UVM methodology Key Responsibilities: ... SoC-level. Lead and manage verification teams, including planning, execution ...
27 days ago