Description: Job Title: Design Verification Engineer Duration: Full time or Contract ... end-to-end solutions for ASIC/FPGA Design both in Digital ... Design & Implementation, Functional Verification, Physical Design, AMS Verification, Layout Design, and circuit ...
27 days ago
Description: Role: Design Verification Engineer Location: Bay Area, CA Hybrid ... Key Responsibilities: * Develop and implement verification plans for complex SoC designs ... using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute ...
22 days ago
Description: Role: Design verification EngineerLocation: Sunnyvale or Austin, USADesign Verification Engineering ServicesTestbench development ...
22 days ago