Description: CAE Design Optimization EngineerRole SummarySupport vehicle design teams across NVH, crash, durability, ... and manufacturing by applying CAE-based optimization ...
18 hours ago
... for a CAE Optimization Engineer (Mid-Level) Job Description: Job Title: CAE Optimization Engineer (Mid-Level ... & ImpactThis role supports company design team across multiple domains NVH ... and manufacturing by applying advanced CAE optimization techniques t
a day ago
Description: Role: Silicon Design Package Engineer Location: Hybrid (Santa Clara, CA ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
22 days ago
Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) ... Description Strong understanding of FPGA design principles and architectures. Proficiency in ...
27 days ago
... , Full Time / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin ...
19 hours ago
Description: Role: Design Verification Engineer Location: San Jose CA/ Irvine ...
13 days ago
... ! We are looking for a Design Verification Engineer to join our growing team ...
29 days ago
Description: Engineer the Future-One Optimization at a Time Step into a high- ... , and design. This opportunity is ideal for a mid-level CAE professional who ... thrives at the intersection of simulation, optimization, and ...
28 days ago
... understanding of FPGA, ASIC, RTL design principles and architecturesProficiency in System ... , Haps)Experience with high-speed I/O design and protocols; knowledge of PCIe ...
a month ago
Description: Cohesive Technologies is a global IT Services & Solutions company providing IT Staffing Services and Application Development Services necessary for technology leaders to deliver business value. We help our people and clients succeed by ...
28 days ago
Description: Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ...
4 days ago
Description: Job Description Onsite, 5 days a week in San Jose Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ...
7 days ago
Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) ... Description Strong understanding of FPGA design principles and architectures. Proficiency in ...
19 hours ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
6 days ago
... Description: Senior Cloud & Infrastructure Engineer Security Platform Focus Location: San ... are seeking a Senior Cloud & Infrastructure Engineer to support our cloud platform ... , and security-minded platform design. The engineer should be capable of stabilizing ...
12 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
21 days ago
... Medical Device Quality Engineer / Senior Sustaining Quality Engineer Needed for Growing Medical ... for a talented Senior Design Quality Engineer / Senior Supplier Quality Engineer! Why join us ...
a month ago
Description: Senior CAE Engineer DurabilityRole SummaryLead durability CAE analysis and validation for vehicle ... , and closures. Work closely with design and testing teams to meet ... of experience in vehicle durability CAE and testing Bachelors or Masters ...
19 hours ago
... experienced ASIC Power Engineer to support power analysis and optimization for next ... ) optimization across RTL and netlist levels, working closely with synthesis, physical design ...
8 days ago
... Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ... and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL ...
8 days ago