Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ...
11 days ago
... : Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... a Senior Staff System IP Design Verification Contractor you will contribute to ... the functional verification of System IP including coherent ...
19 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key ... , Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good ...
12 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ...
11 days ago
... and implement IP/SoC verification plans, build verification test benches to enable ... IP/sub-system/SoC level verification. Develop functional tests based on ... verification test plan. Drive Design Verification to closure based ...
12 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
12 days ago