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Jobs and careers for design verification pcie in San Jose (10 jobs)

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  • TranSquared inc
  • San Jose
Description: Job Title:- ASIC Design Verification Engineer Duration:-12 months+ Location:- ... a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of ... experience in the field of verification. As an Individual Contributor, he ...
14 hours ago
  • Collaborate Solutions, Inc.
  • San Jose
Description: Title: Design Verification Engineer Location: San Jose, CA ... in verificationProven experience with digital design, lab skills, and debugging in ... System verilogtest cases for digital design verification.Perform FPGA designt
14 days ago
  • Datum Software, Inc.
  • San Jose
... an opening for Mixed-Signal Design Verification Engineer with our Client at ... , etc.Good understanding of digital design for mixed signal control loops ...
21 days ago
  • Mirafra Inc
  • San Jose
... : Architect block and full-chip verification environments using HVLs and constrained ... Gate simulations and work with design engineers to verify fixes. Write ...
17 days ago
  • Zachary Piper Solutions, LLC
  • San Jose
... is seeking an FPGA Verification Engineer to work onsite ... per week. The FPGA Verification Engineer will ensure the ... of a cutting-edge digital design environment for FPGA development, ... of the FPGA Verification Engineer include: Design and implement object- ...
16 days ago
  • Zachary Piper Solutions, LLC
  • San Jose
... is seeking an FPGA Verification Engineer to work onsite ... per week. The FPGA Verification Engineer will ensure the ... of a cutting-edge digital design environment for FPGA development, ... of the FPGA Verification Engineer include: Design and implement object- ...
24 days ago
  • Apolis
  • San Jose
Description: Title: Verification Engineer Location: San Jose, CA (5 ... the testbench architecture Strong in Design Functional Verification (SV/UVM) Software (Test ...
18 days ago
  • AIT Global, Inc.
  • San Jose
... : Job Title: Senior ASIC Design Engineer Location: San Jose, CA ... million gate SoC designs onto prototyping platforms, creating design partitions, FPGA ... in block-level RTL design or block or top ... integration. Collaborate with Software, Design, and Verification t
13 days ago
  • Clover Solutions LLC
  • San Jose
... design knowledge Cadence Orcad and Allegro I2C, SMBUS SPI, UART, USB PCIe ...
17 days ago
... timing constraints for complex ASIC designs at the chip level. Your ... , including RTL designers, physical design engineers, and verification teams, to ensure robust ...
4 days ago