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Jobs and careers full-time for senior fpga engineer from the company Data capital inc in Santa Clara (11 jobs)

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  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands ...
5 days ago
  • Data Capital Inc
  • Santa Clara
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands ...
6 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
26 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming ...
10 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands ...
12 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding ( ... Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming ...
16 days ago
  • Data Capital Inc
  • Santa Clara
... verilog coding,UVM 3+ years of FPGA verification experience Strong SystemVerilog programming ...
25 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
18 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
20 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
23 days ago
  • Data Capital Inc
  • Santa Clara
Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ...
24 days ago