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Jobs and careers for fpga verification engineer from the company Data capital inc in Santa Clara (13 jobs)

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... FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
6 days ago
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
9 days ago
... FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
13 days ago
  • Data Capital Inc
  • Santa Clara
... coding,UVM 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
22 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
14 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
17 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
20 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
21 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
23 days ago
  • Data Capital Inc
  • Santa Clara
... Description: 3+ years of FPGA verification experience Strong SystemVerilog programming ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS ...
29 days ago
  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
2 days ago
  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
2 days ago
  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong ...
3 days ago