Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification ...
6 hours ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification ...
2 days ago
Description: Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification ...
6 days ago
... seeking a highly seasoned Lead/Manager Embedded Software Engineer to join our dynamic ... team. In this role, we will lead ...
21 days ago
... Test Engineer to join our growing, remote team. In this lead role ... , etc.). You will lead a team of test engineers and work cross-functionally ...
19 days ago
... -scale deployment. Own the Architecture: Lead the design and implementation of ... Execution: Serve as the project lead, aligning key stakeholders-from Product ...
28 days ago
... , California in 2004 when a visionary engineer, Fred Luddy, saw the potential ...
5 days ago
... . Our Approach to Work We lead wit
15 days ago
... : Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI Location: Santa ...
17 days ago
Description: Title: Agentic AI Engineer Location: Santa Clara, CA Duration: 6+ ... AI Job Description: Ability to lead the design and development using ...
17 days ago
Description: AI engineer Santa Clara - California Contract Job description Ability to lead the ...
18 days ago
... and innovative AI Engineer to join our team and lead the development ...
29 days ago
Description: This company is one of the fastest growing interconnectivity organizations in the world. Their products and services provide modern data center with the right tools for space saving and efficient energy and data connectivity services! This ...
18 days ago
Description: Develop and maintain test benches using UVM/SystemVerilog.Write and debug test cases for functional and performance validation.Identify and resolve design issues in collaboration with engineering teams.Participate in design reviews and ...
27 days ago
... the brightest and most talented engineers and technologists in the industry ... to support the strategy and lead R&D investigations that deliver industry leading ...
4 days ago
... the brightest and most talented engineers and technologists in the industry ... to support the strategy and lead R&D investigations that deliver industry leading ...
9 days ago
... the brightest and most talented engineers and technologists in the industry ... to support the strategy and lead R&D investigations that deliver industry leading ...
10 days ago