Description: Job Title: FPGA Verification Engineer Location: Santa Clara, CA-Onsite ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... in System Verilog and UVM verification methodology. Experience with industry-standard ...
2 days ago
... : Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will work closely with design engineers to develop and execute verification pla
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
5 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
6 days ago
Description: Role: Board Level Testing (BLT) Engineer (Full Time) Location: Santa Clara, ...
2 days ago
... a highly skilled Hardware Design & FPGA Engineer to join our client's advanced ... expertise in FPGA development, hardware board design, and hands-on experience ...
2 days ago
... a highly skilled Hardware Design & FPGA Engineer to join our client s advanced ... expertise in FPGA development, hardware board design, and hands-on experience ...
2 days ago