Description: Title: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA-Onsite ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop forward ...
9 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
3 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
5 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
9 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
11 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
14 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
16 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
18 days ago
... UVM 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
18 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
19 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... on experience with UVM (Universal Verification Methodology) Familiarity with industry- ... standard verification tools (e.g., QuestaSim, Synopsys VCS) ...
26 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
30 days ago
... : 3+ years of FPGA verification experience Strong SystemVerilog programming skills ... experience with UVM (Universal Verification Methodology) Familiarity with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
a month ago
... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
9 days ago
Description: Engineer On Site at Santa Clara , ... Embedded Software 2. Basic knowledge of SoC and Microprocessors 3. 2-5 years of Embedded ... and IntegrationTechnologies:ARM Embedded Software SOC & Microprocessor Embedded Linux AndroidRequired Education ...
13 days ago
Description: Title: Software Engineer - Hybrid Mandatory skills: Java, Ruby, ... architecture,ASIC standard verification tools, languages, flows Description: Responsibilities: Design, build, test ...
6 days ago
... hiring a Hardware Board Failure Analysis Engineer Position type: Contract Duration: Long ... ) As a Hardware Board Failure Analysis Engineer, you will need: Must-have ... , 11 PM to 8 AM.Conduct verification of the module/ IP functionality
10 days ago
... Title: Materials Science AI Engineer Job Location: Santa Clara, ... Range: $60hr - $65hrResponsibilities: Design, develop and deploy multi-modal ... solve material physics and design problems.Aggregate, process, ... modeling and analysis.Design, develop and maintain ...
5 days ago
... looking for a AI Engineer for our client in Santa ... CA Job Title: AI Engineer Job Location: Santa Clara ... - $65hrThe Generative AI Design Engineer will design, develop, and optimize generative ... as content creation, product design, intelligent automation, and ...
6 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
19 days ago