... , Engineering Group > ASICS Engineering General Summary: A SOC Physical Design Engineer plays a crucial role ... requires strong knowledge of physical design tools (like Cadence or Synopsys ...
19 days ago
... Role Title: Sr. Physical Design Engineer / Sr. Silicon Design Engineer Location: Santa Clara, California ... ) THE ROLE: This is a Physical Design Engineering role that will require ... to take the design from RTL to GDS with ...
8 days ago
... looking for Senior Silicon Design Engineer for our client ... Job Title: Senior Silicon Design Engineer Job Location: Santa Clara ... engineer will work on high-speed multi-gigabit SerDes PHY designs ... control logic applications, automated design flows for clock tree ...
8 days ago
... looking for Senior RTL Design Engineer for our client in ... Job Title: Senior RTL Design Engineer Job Location: Santa Clara, ... .86hr Responsibilities:Perform RTL design of digital components in Verilog ... to improve/automate the design process.Preferred Experience: ...
21 days ago
... are looking for Senior RTL Design Engineer for our client in Santa ... , CA Job Title: Senior RTL Design Engineer Job Location: Santa Clara, CA ... of IP subsystems.Perform RTL design of digital components.Work with ...
23 days ago
Description: Title: Physical Design Engineer (8-15 Years Experience) Location Santa ... Fulltime Job Description: As a Physical Design Engineer, you will play a crucial role ... and Cadence Innovus to optimize designs for performance, power, and area ...
20 days ago
... add an experienced Lead Mechanical Design Engineer to work within its Server ... , California. As a member of this design team, you will have the ...
12 days ago
... MedTech, is recruiting for a Primary R&D Design Engineer, located in Santa Clara, CA ...
12 days ago
... Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading ... all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or ...
11 days ago
... of engineers, using the latest verification practices, to verify the digital design ... tests to verify the SOC design at the system or block ...
29 days ago
... , Engineering Group > ASICS Engineering General Summary: The Digital ASIC Design Team is currently ... verification of DFT/DFD (Design for Test/Design for Debug) techniques for ... low power, multi voltage designs. The candidate should have solid ...
13 days ago
... Engineer will develop ATE test solutions, both hardware and software, for design ... management, analog and mixed signal ASICs designed by Qualcomm. We work with ... Design, System, Foundry, Program Management, Yield, ...
4 days ago
... quality metrics in complex, hierarchical designs and automating that process for ... development of pre-production synthesis (Design Compiler) and STA (Primetime) flows ...
26 days ago
... :Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading ... all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and ... power of GPU cores. Qualcomm Engineers collaborate with
8 days ago
... :Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading ... all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and ... power of GPU cores. Qualcomm Engineers collaborate with
29 days ago
... Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading ... all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and ...
13 days ago
... is a leading supplier of key ASICs and system SW that power ...
11 days ago
... a UEFI/BIOS Firmware Engineer with background in systems architecture ... responsible for the hardware design, development and delivery of ... and Oracle's on-premise engineered systems. This candidate will ... oriented environment to architect, design and implement U
12 days ago
... a UEFI/BIOS Firmware Engineer with background in systems architecture ... responsible for the hardware design, development and delivery of ... and Oracle's on-premise engineered systems. This candidate will ... oriented environment to architect, design and imple
12 days ago
... to join a world-class Digital Design Engineering group and take imaginative ... real world. You'll help design the tools that allow us ... extraordinary opportunity for Standard Cell Design Methodology a
22 hours ago