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Jobs and careers for design verification engineer in Santa Clara (3 jobs)

Lead fpga verification engineer with uvm /verilog system-active requirement
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
3 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
5 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
9 days ago

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