Description: Role: Silicon Design Package Designer Location: Santa Clara, CA ... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
3 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, ... specialized in semiconductor packaging design, requiring strong EDA tool ... ). Technical Expertise: o Multi-layer package design experience. o Understanding of substrate manufacturing ...
3 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, CA ... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
3 days ago
... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA). Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ... Design Rules and Assembly Rules. ...
3 days ago
Description: Role: Silicon Design Package Designer Location: Santa Clara, CA ... specialized in semiconductor packaging design, requiring strong EDA tool ... PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing ...
3 days ago
Description: Role: Package Designer (Semiconductor , Silicon) Location: Santa Clara, ... specialized in semiconductor packaging design, requiring strong EDA ... Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing
3 days ago
Description: USB Systems Design Engineer The job is 100% ... Design Engineer, you will be developing, executing and debug USB post silicon ...
27 days ago
... performance and reliability. Key Responsibilities Design, develop, and execute power measurement ...
24 days ago
Description: Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( ...
25 days ago
... on silicon anode materials and battery cells Design and develop advanced silicon anode ...
3 days ago
... : Pay Range: $82hr - $103hrThe DFT Design Engineer will be part of ... the DFT design team responsible for scan/ATPG ... test engineering teams for successful silicon bring-up of sc
19 days ago
... . Job Responsibilities Experience with 2.5D package design and development like CoWoSStrong expertise ... tools like Cadence APDUnderstanding IC package design requirements for high speed interfaces ...
6 days ago
... Tier 1 clients // Growing + Excellent compensation package + generous Bonus structure! This Jobot ... with a leading company that develops, designs, and manufactures highly engineered materials ...
24 days ago