Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
a day ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
6 days ago
Description: Position: Principal Engineer, Design Verification (NPU) Location: Mountain View ... Project description The Principal Design Verification Engineer, within the NPU Hardware ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
Description: Title: Principal Engineer, Design Verification (NPU) Location: Mountain View, ... Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... experience in AI accelerator verification and automotive safety standards. ...
3 days ago
... Description: Project descriptionThe Principal Design Verification Engineer, within the NPU Hardware & ... broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
a month ago
... IP is hiring for a Verification Engineer to join their high-performance ... team! Responsibilities include: - Developing verification environments using System Verilog and ... UVM - Designing verification components and behavioral models - ...
16 days ago
$85
$90
an hour
Description: SerDes Validation Engineer San Jose, CA (100% Onsite) 6 + ... Have Skills: SerDes HW validation, PCIe & 800G Ethernet, Python, firmware Role ... + 5 yrs experience Strong SerDes validation (PCIe/Ethernet) Python scripting & automation Firmware ...
13 days ago
Description: Job Title: Software Engineer - PCIe Driver Development Location: San Jose, ...
14 days ago
Description: PCB HW Validation Engineer We are seeking an experienced ... PCB Hardware Validation Engineer to validate printed circuit board ... subsystems, including PCIe and I2C. Scope: Perform PCB functional verification to confirm ...
10 days ago
Description: Hi, Role: Firmware Validation Engineer (System Level) Location: Santa Clara, ... + Must Have Skills Firmware Validation Engineer Skill 1 10 + Years of exp ... high-speed interfaces such as PCIe, UART, and UMA.
a day ago
... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... engineer will be working on cutting-edge technologies such as LPDDR5X, PCIe ...
7 days ago
... looking for Senior Hardware Engineer for our client in ... CA Job Title: Senior Hardware Engineer Job Location: San Jose, ... - $88.86hrThe Senior Hardware Engineer will be responsible for validating ... interfaces with a focus on PCIe and 800G Ethernet technologies. ...
13 days ago
Description: Position: Hardware Design Engineer (Architect) Location: San Jose, USA ... , oscilloscopes, multi-meters, signal generators, PCIe Gen5/6, LPDDR5/6 5 - 8 years of experience ...
2 days ago
... & Power Integrity Engineer to support high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe ...
7 days ago
... : Position: SOC Post Silicon Validation Engineer Exp: 10+ years Location: San ... of SoC peripherals, including LPDDRx, PCIe, I2C, and qSPI.Manage and ...
8 days ago
Description: Signal Integrity Engineer- Power Integrity experience is a plus. ... with SERDES interfaces such as PCIe, PAM4, USB. Experience with Characterization ...
9 days ago
Description: Position: System Level Test Engineer Location: San Diego, USA Key ... , bench testing, TPUs, CPUs, GPUs, PCIe, Ethernet , C#, C/C++, PERL, Python, .NET framework ...
14 days ago
Description: Title: RTL Design Engineer - Onsite Mandatory skills: FPGA, design, ... , data, control path, implementing interfaces, PCIe, Gen 6, Gen 7, CXL, UAL, Ethernet ...
17 days ago
Description: Position: System Level Test Engineer Location: San Diego, USA Duration: ... , bench testing, TPUs, CPUs, GPUs, PCIe, Ethernet, C#, C/C++, PERL, Python, .NET framework ...
17 days ago