Description: Senior Design Verification Engineer SV/UVM Contract Long Term ... francisco BayArea Key ResponsibilitiesOwn the verification of complex IP/subsystems using ...
2 days ago
Description: Position Title: Design Verification Engineer Location: Mountain View, CA - Onsite ... Build UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
3 days ago
Description: Systems Hardware Architect / Design Verification Engineer Mountain View, CA NO 14+ ... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
4 days ago
... an immediate requirement for a Design Verification Engineer with a client in Mountainview, CA ... me at . Job Title: Design Verification Engineer Location: Mountain View, CA (Working ...
8 days ago
... is looking for a Senior System Verification Engineer to join our Emulation division ...
15 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ...
17 days ago
Description: NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of ... arm is a hub for all silicon and system-level feature development ...
19 days ago
... and implement IP/SoC verification plans, build verification test benches to enable ... IP/sub-system/SoC level verification. Develop functional tests based on ... verification test plan. Drive Design Verification to closure based ...
18 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
17 days ago
... requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC ...
8 days ago
Description: NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep ...
15 days ago
Description: Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus
11 days ago
Description: Vendor referrals and C2C will not be considered. Project, main deliverables: Support FPGA debug, simulation and test activities for existing platforms for defined features/escalations Create updated RTL design for identified issues and block ...
22 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) ... : Engineering Required Skills: Pre-silicon verification / UVM methodology Key Responsibilities: ... SoC-level. Lead and manage verification teams, including planning, execution ...
11 days ago
Description: Job Title: PCIe Engineer (Peripheral Component Interconnect Express) ... : Engineering Required Skills: Pre-silicon verification / UVM methodology Key Responsibilities: ... SoC-level. Lead and manage verification teams, including planning, execution ...
15 days ago
... of sectors. We seek Silicon Solutions Engineers who are passionate about what ... inventions. As part of the Silicon Solutions Team, we are responsible ...
20 days ago
Description: Design Verification CPU Core & Block Looking for a ... feature/test plan verification engineer responsible for ISA & microarchitectural verification. This will be ... Santa Clara, CA. Scope: Functional verification with emphasis on core level ...
23 days ago
... is seeking outstanding Senior Design Verification Engineers with a specialty in tools and ...
7 days ago
Description: Design Verification Engineer: Location: Sunnyvale, CA Onsite role. ...
23 days ago
Description: Role: CAD/EDA Engineer Silicon Design/Verification Infrastructure Location: San Francisco, CA / ... SoC/IP design and/or verification infrastructure development. Proficiency in modern ...
17 days ago