Description: Job Title: Design Verification Engineer Duration: Full time or Contract ... end-to-end solutions for ASIC/FPGA Design both in Digital ... Design & Implementation, Functional Verification, Physical Design, AMS Verification, Layout Design, and circuit ...
a month ago
Description: Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) ... and implement IP/SoC verification plans, build verification test benches to enable ... tests based on verification test plan Drive Design Verification to closure based ...
a day ago
Description: Role: Design Verification Engineer Location: Bay Area, CA Hybrid ... Key Responsibilities: * Develop and implement verification plans for complex SoC designs ... using SystemVerilog and UVM (Universal Verification Methodology). * Write and execute ...
23 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
3 hours ago
Description: Role: Design verification EngineerLocation: Sunnyvale or Austin, USADesign Verification Engineering ServicesTestbench development ...
23 days ago