Description: Job Title: Senior Design Verification Engineer (SystemVerilog / UVM) Location: San ... are seeking an experienced Design Verification Engineer with strong expertise in ... ASIC/RTL designs and developing robust verification environments across ...
6 days ago
... following positions in Sunnyvale, CA Design Verification Engineer: Collaborates with researchers, architects, and ... designers to establish comprehensive verification strategies for a variety of core ...
7 days ago
Description: Role: Senior/Staff VLSI Engineer Ethernet FEC DV Duration: 12+ ... a highly skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward ... role, you will own the verification of advanced FEC IP cores ...
18 days ago
Description: RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge ... Working experience with digital logic design and verification Practical experience in D2D ...
13 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
26 days ago
Description: Role: Principal Engineer, Design Verification (NPU) Location: Mountain View ... Contract Project description The Principal Design Verification Engineer, within the NPU Hardware ... a broad background in design verification and complex digital system ...
3 days ago
Description: Title: Principal Engineer, Design Verification (NPU) Location: Mountain View, ... 5% Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... a broad background in design verification and complex digital system ...
a month ago
... Title: Lead SoC/Sub-System Design Verification Location: Sunnyvale, CA (Onsite) ... and highly motivated Lead Engineer to drive the design verification of complex System ... will lead a team of verification engineers, define verification strategies, and ensure the ...
17 days ago
Description: Role: Design Verification Lead Location: Sunnyvale onsite ... System Design Verification About the Role We are seeking an experienced Design Verification Lead ... to drive SoC-level verification strategy, lead ...
14 days ago
... products. Understand design specifications and interact with design engineers to identify verification scenarios. Create ... test plans, constrained-random verification environments ...
17 days ago
... router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test ... plans, constrained-random verification environments ...
19 days ago
... We are seeking a talented AMS Verification Engineer. If you have experience with ... high-speed mixed-signal IP verification, including protocols like PCIe, USB ... aligned with design specs and standards Architect and develop verification testbenches using ...
18 days ago
... Description: Job Title: FPGA Verification Engineer Location: Mountain View, CA ... design principles and architectures. Proficiency in System Verilog and UVM verification ... methodology. Experience with industry-standard verification tools ...
5 days ago
... : Associate ASIC and/or FPGA Design and Verification Engineer Company: Boeing Space, Intelligence ... multiple ASIC and/or FPGA Design and Verification Engineers to join us as ...
11 days ago
... positions in Sunnyvale, CA ASIC Engineer, Design Verification: Develop functional tests based on ... verification test plan. (ref. code REQ- ...
12 days ago
... looking for Firmware Development and Verification Engineer for our client in ... Job Title: Firmware Development and Verification Engineer Job Location: Markham, ON Job ... are seeking a Power Management Firmware Engineer to design, implement, and validate power ...
3 days ago
Description: Title: PCIe Verification Engineer Location: Hybrid in San Jose ... Summary Verify PCIe Switch / Retimer designs across Gen4/Gen5/Gen6 using ... Develop and execute PCIe verification plansBuild UVM-based verification environmentsVerify PCIe protocol
13 days ago
Description: Position:EDVT(Electrical Design Verification Test) Engineer Location:San Jose, CA ... in a project team of engineers involved in specifying, designing, ... closely with hardware design engineers, software/diagnostic engineers, and manufacturing test ...
4 days ago
Description: Role: PCIe Verification Engineer Position Type: Contract Location: San ... pre-silicon verification of next-generation PCIe Switch and Retimer designs across ...
25 days ago
Description: Title: Senior Systems Software Verification Engineer Location: Palo Alto, CA (5 Days ... for a Senior Embedded Software Validation Engineer to join their team working ... a hands-on role where youll design and execute system- and component ...
3 days ago