... : Description We are seeking a Wireless Test Automation Engineer with experience testing performance ... of wireless devices in a lab ... hands-on experience with common wireless test equipment, ancillary lab ...
10 days ago
... Description: We are seeking a Wireless Test Automation Engineer with experience testing performance ... of wireless devices in a lab ... hands-on experience with common wireless test equipment, ancillary lab ...
10 days ago
... skilled and independent RF Wireless Connectivity Test Engineer to join our team ... the robust performance of critical wireless technologies. The ideal candidate will ...
4 days ago
... human life on Mars. WIRELESS MODEM VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX ...
6 days ago
Description: Company Description To comply with U.S. federal government requirements, U.S. citizenship is required for this position Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, ...
11 days ago
Description: Sr. SOC Analyst (can be from a Developer, ... least 4 years of experience as a SOC analyst, incident response experience, etc ... - Experience installing network security devices (FW, IDS/IPS, etc.) and servers ...
43 minutes ago
Description: Sr SoC Gate-Level Simulation (GLS) Engineer In need of ... Simulation Engineer to support complex System-on-Chip (SoC) development ... timing, and power across SoC subsystems. You'll work ... methodologies for high-performance SoC projects Run gate-level ...
6 days ago
Description: Digital SoC Design Verification Principal Engineer/Manager 140-225K (+ Pre-IPO ... Digital SoC Design Verification Principal Engineer/Manager to lead a team of engineers in ...
10 days ago
... is looking for Design Verification Engineer SOC at San Jose, CA Below ... the details: Title : Design Verification Engineer SOC Location : San Jose, CA TOP ... SkillsExperience: 8+ years of experience in SOC, SystemVerilog/UVM methodologyExperience in EDA ...
10 days ago
Description: Title: ASIC Verification Engineer - Hybrid Mandatory skills: UVM, UVM ... verification, UVM environment, AISC, SOC, AISC verification, SOC verification, DV tools, DV ... Synopsys, Verdi, System Verilog, IP, I/O SOC, UVM test bench development, design ...
26 days ago
... a skilled and experienced IR Analysis Engineer to join our team, specializing ... -on-Chip (SoC) and Interposer designs. As an IR Analysis Engineer, you ... analysis methodologies, with a focus on SoC and Interposer designs. Responsibilities Perform ...
5 days ago
Description: Sr. Network Engineer Ubiquiti Wireless Deployment Location: Gilroy, CA (Hybrid 3-4 ... from the current Extreme Networks wireless infrastructure to a fully deployed ... and optimized Ubiquiti wireless solution across all the Client ...
6 days ago
... with on test plans for SOC-level or full-chip features ...
3 days ago
... : Job Title Sr. Package Design Engineer ASIC/SOC Job Location: San Jose ... The Role: Sr. Package Design Engineer We are seeking a highly experienced ... Package Design Engineer with 7+ years of hands-on
4 days ago
Description: Job Title: Physical Design Engineer Custom ASIC / SoC Hybrid San Jose, CA ... available Position Overview Physical Design Engineer: We are seeking a hands-on ...
4 days ago
... Engineer to work on developing next-generation custom System-on-Chip (SoC ... cross-functional teams to optimize SoC design and developmen
5 days ago
Description: DFT/DFD Verification Engineer Advanced SoC Projects We are looking for a ... -Test / Design-for-Debug Verification Engineer focused on validating sophisticated test ...
6 days ago
$75
$80
an hour
... RTL Design Engineer with a strong background in digital design and SoC development ... IP development to drive successful SoC tapeouts. You will work closely ...
11 days ago
... : Wireless Test Engineer for Global Device Company We are seeking a detail-oriented Wireless ... end-to-end validation of wireless components for next-generation infotainment ...
12 days ago
... for a senior level RTL design engineer. As a part of the design ... edge I/O SoC in 3 nm processes. This DFX RTL XXgn Engineer is expected ... to contribute in : Implementation of SOC DFT ...
26 days ago