Description: Package Design Engineer in the US, please share ... Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
7 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
a day ago
Description: Position: IC Design Engineer Location: San Jose, CA & Chandler, ... looking for an experienced IC Package Design Engineer to develop creative, efficient, and ... Description: Create Netlists and BGA designs as per input specifications. Conduct ...
25 days ago
... CA Job Description: FPGA/RTL Design Engineer to design, implement, and validate digital ... development using RTL languages, FPGA design tools, and simulation environments, while ... of our products. Key Responsibilities Design & Implementation: Develop RTL code ( ...
7 days ago
... RTL Design Engineer Location: San Jose, CA (Onsite) FPGA/RTL Design Engineer to design, ... development using RTL languages, FPGA design tools, and simulation environments, ... of our products. Key Responsibilities Design & Implementation: Develop RTL code ...
7 days ago
... CA Job Description: FPGA/RTL Design Engineer to design, implement, and validate digital ... development using RTL languages, FPGA design tools, and simulation environments, while ... of our products. Key Responsibilities Design & Implementation: Develop RTL code ( ...
7 days ago
... CA Job Description: FPGA/RTL Design Engineer to design, implement, and validate digital ... development using RTL languages, FPGA design tools, and simulation environments, while ... of our products. Key Responsibilities Design & Implementation: Develop RTL code ( ...
7 days ago
... for Senior ASIC/RTL Design Engineer for our client in ... Job Title: Senior ASIC/RTL Design Engineer Job Location: San Jose, ... $64.68hr - $81.42hrThe RTL Design Engineer will be responsible for leading ... and participating in the design of cutting-edge SoCs ...
26 days ago
Description: Role: Hardware Systems Design Engineer Location: San Jose, CA (Onsite 3-4 ... ) AI/ML processors. Board-Level Design: Lead PCB layout and SI ... software issues. System Bring-up: Design boards intended for ASIC bring ...
5 days ago
Description: Position: Hardware Systems Design Engineer Location: San Jose, CA (Onsite) ... software issues.System Bring-up: Design boards intended for ASIC bring ...
5 days ago
Description: Design & Implementation: Develop RTL code (Verilog, ... functional simulation, debug FPGA designs, and resolve design issues. Validation & Testing: Create ... unit tests, example designs, and demos; ensure readiness of ...
6 days ago
... resume along with LinkedIn Position : Package Designer Location: San Jose, CA ... creative and cost-effective IC package designs. Job Description:Netlist & BGA creationSubstrate ...
6 days ago
Description: Title: Package Designer (Onsite - San Jose)Experience: 5+ ... creative and cost-effective IC package designs. Job Description:Netlist & BGA creationSubstrate ...
25 days ago
Description: Role Name : Hardware Engineer/Network System Design Architect Location : San Jose, ... Overview: As a Hardware Engineer/Network System Design Architect, you will play ... detailed discussions with their hardware design engineers, and transferring
14 days ago
... Position Overview: As a Network System Design Architect, you will play a pivotal ... detailed discussions with their hardware design engineers, and transferring key insights and ... background in signal integrity (SI) design, particularly in the realm of ...
28 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
a day ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
3 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
5 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
5 days ago
Description: Job Title: Package Designer Location: San Jose CA / ... strategies and via structures. Substrate design experience for RF, digital, high ...
6 days ago