... are looking for a USB Systems Design Engineer for our client in Santa ... , CA Job Title: USB Systems Design Engineer Job Location: Santa Clara, CA ... .11hr - $76.74hrThe SOC Validation Engineer will be responsible for driving ...
22 days ago
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
18 days ago
... experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop ... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to ...
21 days ago
... performance validation.Identify and resolve design issues in collaboration with engineering ... teams.Participate in design reviews and contribute to verification ... of FPGA, ASIC, and RTL design.Hands-on experience with SystemVerilog ...
20 days ago
Description: Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core ...
20 days ago
... engineer Santa Clara - California Contract Job description Ability to lead the design and ... APIs and secure workflowsEnsure system designs meet enterprise requirements for security ...
8 days ago
... deployment. Own the Architecture: Lead the design and implementation of large-scale ... Execution: Serve as the project lead, aligning key stakeholders-from Product ...
18 days ago
... deployment. Own the Architecture: Lead the design and implementation of large-scale ... Execution: Serve as the project lead, aligning key stakeholders-from Product ...
27 days ago
Description: Title: Agentic AI Engineer Location: Santa Clara, CA Duration: 6+ ... Job Description: Ability to lead the design and development using NVIDIA BluePrints ...
7 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
7 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
7 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
8 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
11 days ago
... are looking for DFT / ATPG Engineer for our client in Santa ... , CA Job Title: DFT / ATPG Engineer Job Location: Santa Clara, CA ... : Pay Range: $82hr - $103hrThe DFT Design Engineer will be part of the ... DFT design team responsible for scan/ATPG ...
14 days ago
... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and ... have a strong background in design debugging and a deep familiarity ... deliverables. Key Responsibilities: Design and develop RTL for
19 days ago
... : Job Title FPGA RTL design and Board validation Location: ... a highly skilled Senior FPGA Design Engineer with 7 to 15 years ... of experience in RTL design, IP design and development, and FPGA ... have a strong background in design debugging and a deep familiarity ...
20 days ago
Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI Location: Santa ... understanding of FPGA, ASIC, RTL design principles, and architectures. Proficiency in ... etc. Knowledge of high-speed I/O design and protocols (PCIe, I2C, SPI ...
7 days ago
... experienced FPGA Verification Engineer to verify complex FPGA designs. You will develop ... validation. .Identify and resolve design issues in collaboration with engineering ... teams. .Participate in design reviews and contribute to verification ...
28 days ago
... Lead/Architect Location : Santa Clara, CA (Hybrid) Full Time Key Responsibilities Design ... technologies and recommend adoption strategies.Lead modernization initiatives including cloud migration ...
12 days ago
... seeking a highly seasoned Lead/Manager Embedded Software Engineer to join our dynamic ... team. In this role, we will lead ...
12 days ago