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Jobs and careers for ams bench test in Santa Clara (8 jobs)

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Lead Digital Design Verification Engineer/FPGA

  • Data Capital Inc
  • Santa Clara
... and maintain test benches using UVM/SystemVerilog.Write and debug test cases for ...
12 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
Description: Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and ... debug test cases for functional and performance ...
14 days ago

FPGA Design Engineer

  • Data Capital Inc
  • Santa Clara
Description: Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and ... debug test cases for functional and performance ...
14 days ago

FPGA Design Engineer

  • Data Capital Inc
  • Santa Clara
... products. Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and ... debug test cases for functional and performance ...
15 days ago

FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... products. Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and ... debug test cases for functional and performance ...
15 days ago

FPGA Validation Lead Engineer

  • Data Capital Inc
  • Santa Clara
... products. Responsibilities: .Develop and maintain test benches using UVM/SystemVerilog. .Write and ... debug test cases for functional and performance ...
22 days ago

Lead FPGA Verification Engineer

  • Data Capital Inc
  • Santa Clara
... products. Responsibilities: Develop and maintain test benches using UVM/SystemVerilog.Write and ... debug test cases for functional and performance ...
26 days ago

FPGA Verification Engineer

  • Info Dinamica Inc
  • Santa Clara
... FPGA designs. Create and maintain test benches using industry-standard verification methodologies ... (e.g., UVM, SystemVerilog). Write and debug test cases to verify functionality, perf
27 days ago
FPGA Verification Engineer FPGA Design Engineer FPGA Validation Lead Engineer Lead FPGA Verification Engineer

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